Interrupts and timers
Introduced| English | Meaning |
|---|---|
| interrupt/ˈɪntərʌpt/ | An event request that can transfer execution to a handler when enabled and accepted by the processor. |
| interrupt service routine/ˈɪntərʌpt ˈsɜːvɪs ruːˈtiːn/ | A routine invoked to handle an accepted interrupt, after which execution may return to the interrupted context. |
| timer | A hardware counter in a microcontroller used to measure time or produce regular events. |
| prescaler | A counter that divides a clock frequency down before it reaches a timer. |
A week or a year
- The sensor node must run for a year on one battery. If the CPU polls all day, the battery is empty in about a week.
- Interrupts let the CPU sleep until something needs it. This lesson shows how they work and what they cost.
The interrupt
- An interrupt 中断 stops the main program where it is. The hardware saves the return state and jumps to an interrupt service routine 中断服务程序 (ISR).
- The NVIC (nested vectored interrupt controller) picks the ISR and ranks priorities. The ISR runs, clears its flag and returns.
Put the handling of one interrupt in order.
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Save, jump, serve, clear, return. Forget the clear and the last step never comes.
The timer
- A timer 定时器 is a counter clocked through a divider, the prescaler 分频器. In the STM32-style upcounter used here, it raises an update event when the count wraps from ARR back to zero; an enabled interrupt can then call the ISR.
- Two divisions turn a fast clock into a slow, exact tick.
The timer equation
- The interrupt rate is $f_{\text{int}} = \dfrac{f_{\text{clock}}}{P R}$, where $P = PSC + 1$ and $R = ARR + 1$.
- The stored registers PSC and ARR are 16-bit values, at most 65 535. Their divider factors can reach 65 536 because zero is counted too. Check that the registers fit and that $PR = f_{\text{clock}}/f_{\text{int}}$.
A timer runs from 84 MHz with prescaler 84 and reload 1000. What is the interrupt rate in Hz?
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$84 \times 10^{6} / (84 \times 1000) = 1000$ Hz: a 1 ms tick, with both factors inside 16 bits.
Worked example: a 1 Hz heartbeat
- From 84 MHz, divider factor 8400 gives 10 kHz. A further factor of 10 000 gives exactly 1 Hz: write PSC = 8399 and ARR = 9999.
- Check: both stored values fit 16 bits, and $8400 \times 10\,000 = 84 \times 10^{6}$. Divider factor 84 000 would need PSC = 83 999, which does not fit.
The divider factor includes the zero count
$f_{update}=f_{clock}/[(PSC+1)(ARR+1)]$
Start with the worked 84 MHz to 1 Hz heartbeat. Divider factors 8400 and 10000 require stored PSC = 8399 and ARR = 9999 in this STM32-style upcounter. Advance exact clock edges, counter ticks and update events, then use a small 4 × 5 example to see zero counted. Compare writing the factors directly to the registers and observe the changed rate.
From an 84 MHz clock, prescaler 4200 and reload 20 000 give an interrupt at
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$4200 \times 20\,000 = 84 \times 10^{6}$, the clock, so exactly 1 Hz; and 20 000 ≤ 65 535 fits a 16-bit reload.
Prescaler 1 and reload 84 000 is a valid 1 kHz design on 16-bit timer registers.
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The product is right, but 84 000 is more than 65 535, so the reload does not fit. Prescaler 84 with reload 1000 works.
Worked example: interrupt or poll?
- An ISR with 12 cycles of entry, 30 instructions and 10 cycles of return costs 52 cycles, or 0.62 µs at 84 MHz.
- That cost is paid on every event: 0.06% of the CPU at 1 kHz of events, but 62% at 1 MHz. At very high rates, polling wins.
A 52-cycle ISR at 84 MHz, serving 1 MHz of events, uses about
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$52 \times 10^{6}$ cycles a second out of $84 \times 10^{6}$ is 62%. The same ISR at 1 kHz uses only 0.06%: the event rate decides.
The same 52-cycle ISR serves 10 kHz of events at 84 MHz. What percentage of the CPU does it use? Give 1 decimal place.
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$52 \times 10\,000 = 520\,000$ cycles a second; $520\,000 / 84 \times 10^{6} = 0.62\%$.
Three common slips
- Forgetting to clear the flag. The CPU returns and enters the ISR again, for ever.
- Long ISRs. Do the minimum, set a flag, and let the main loop do the work.
- Reading a 16-bit timer in two halves. A carry between the reads corrupts the value; read the high byte twice or use a latch.
An ISR that forgets to clear its interrupt flag causes
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The flag still shows pending when the ISR returns, so the CPU jumps straight back in. Clear the flag and keep the ISR short.
Recap
- Interrupt: vector, short ISR, clear the flag.
- Timer: divide $f_{\text{clock}}$ by $(PSC+1)(ARR+1)$; check the stored register values and the divider product.
- Interrupts win at low event rates; polling wins at very high ones.